1. Field of the Invention
The present invention relates to a MOS semiconductor device having a p-channel MOSFET (p-MOSFET) and n-channel MOSFET (n-MOSFET) formed on different crystal planes, and a method of fabricating the same.
2. Description of the Related Art
To increase the operating speed of a complementary MOSFET (C-MOSFET) having both a p-MOSFET and n-MOSFET formed on a single-crystal Si substrate, the mobilities of carriers flowing through channel portions must be kept high. However, the crystal plane on which the highest carrier (i.e., hole) mobility can be achieved for the p-MOSFET is different from the crystal plane on which the highest carrier (i.e., electron) mobility can be obtained for the n-MOSFET. That is, for a Si substrate, a surface crystal plane which achieves the maximum electron mobility is (100), whereas a surface crystal plane which achieves the maximum hole mobility is (110) (H. Irie et al., IEDM Tech. Dig. pp. 225-228, 2004). Thus, simultaneous optimization of the operation speeds of both types of the MOSFETs is unattainable if one uses the single-crystal Si substrate (which has a unique and definite surface crystal orientation). Accordingly, the high-speed operation of the entire C-MOSFET function must be significantly compromised on the conventional single-crystal Si substrate, no matter which crystal plane the substrate surface is oriented to.
Recently, therefore, to increase the operating speed of MOSFETs of the both polarities in a C-MOSFET circuit, a method called Direct Substrate Bonding (DSB) is proposed, where a thin crystalline Si layer having different crystal orientation from a host crystal Si substrate is directly bonded to the substrate surface (C. Sung et al., IEDM Tech. Dig. pp. 235-238, 2005). Subsequent selective amorphization of specific regions and consequent re-crystallization of the amorphized regions converts the surface orientation of the intended regions to the one identical to the host Si substrate (i.e., the surface orientation different from that of the thin surface crystalline Si layer). In this way, by forming both (100) and (110) surface planes on a complex Si substrate (DSB substrate), the method maximizes the mobilities of MOSFETs of the two polarities simultaneously.
On the other hand, shrinking dimensions of C-MOSFETs requires commensurate shallowing of the junctions in the source/drain regions. Of course, in order to counter the increase of the electrical resistance of the source/drain regions associated with these ever-shallowing source/drain junctions and also to ensure the high-speed device operation, silicidation (i.e., a compound formation between metallic material and silicon) of source/drain regions is an indispensable option for LSI fabrication.
Unfortunately, however, application of the silicide technique to the DSB substrate comes to encounter difficult problems. Since a thin crystalline Si layer having different crystal orientation from the host Si substrate is directly bonded to the substrate, naturally, substantial amounts of crystal defects associated with the lattice mismatching are formed at the shallow bonding plane just below the substrate surface (i.e., close to the pn junctions of the source/drain region). The presence of the crystal defects greatly promotes diffusion of metal atoms (transient enhanced diffusion). Accordingly, metal atoms released from the silicide layer rapidly diffuse and readily reach the pn junctions of the source/drain regions. Because the metal atoms can form gap states in the Si substrate and constitute efficient generation-recombination (GR) centers, the metallic outburst induced by the crystal defects at the shallow bonding plane generates significant leakage current and eventually impair the proper function of the C-MOSFET devices formed on the DSB substrate.
Even an elevated source/drain structure may not provide much help to alleviate this problem. The thickness of a Si layer to be additionally formed by the selective Si growth technique depends on the surface orientation of the substrates. Thus, on the DSB substrate, the thickness comes to change in accordance with the polarity of the MOSFET. Resulting non-uniform and inhomogeneous Si layer necessitates excessive formation of the additional Si layer to secure minimum thickness of the elevated source/drain Si layer. The excessive formation of the additional Si layer leads to an unduly thick layer almost equal to the height of a gate electrode, which is totally intolerable in terms of an unacceptable increase of the capacitive coupling between source/drain regions and the gate electrode. Of course, thinner Si layer formation in a region adjacent to the gate electrode greatly spoils the original intention of leakage suppression by increasing the thickness of the source/drain electrodes.
As described above, the conventional method which increases the operating speed of a C-MOSFET by using a DSB substrate has the problem that the diffusion of metal atoms released from the silicide layer causes significant junction leakage. In addition, even when an elevated source/drain structure is formed in order to solve this problem, uniform and homogeneous film formation is extremely difficult. Therefore, the effective leakage suppression cannot be achieved without forming an intolerably thick Si layers by the selective Si growth.